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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2000 2m-bit cmos static ram 256k-word by 8-bit extended temperature operation mos integrated circuit pd442000a-x data sheet document no. m14669ej7v0ds00 (7th edition) date published october 2002 ns cp (k) printed in japan the mark shows major revised points. description the pd442000a-x is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) cmos static ram. the pd442000a-x has two chip enable pins (/ce1, ce2) to extend the capacity. and battery backup is available. the pd442000a-x is packed in 32-pin plastic tsop (i) (normal bent) and 32-pin plastic tsop (i) (reverse bent). features ? 262,144 words by 8 bits organization ? fast access time : 55, 70, 85, 100, 120 ns (max.) ? low voltage operation : v cc = 2.7 to 3.6 v (-bb55x, -bb70x, -bb85x) v cc = 2.2 to 3.6 v (-bc70x, -bc85x, -bc10x) v cc = 1.8 to 2.2 v (-dd85x, -dd10x, -dd12x) ? low v cc data retention : 1.0 v (min.) ? operating ambient temperature : t a = ?25 to +85 c ? output enable input for easy application ? two chip enable inputs : /ce1, ce2 pd442000a access time operating supply operating ambient supply current ns (max.) voltage temperature at operating at standby at data retention vcma (max.) a (max.) a (max.) -bb55x, -bb70x, -bb85x 55, 70, 85 2.7 to 3.6 ? 25 to +85 30 note 21 -bc70x, -bc85x, -bc10x 70, 85, 100 2.2 to 3.6 30 -dd85x, -dd10x, -dd12x 85, 100, 120 1.8 to 2.2 15 1.5 note cycle time 70 ns, -bb55x : 35 ma
data sheet m14669ej7v0ds 2 pd442000a-x ordering information part number package access time operating operating ns (max.) supply voltage temperature vc pd442000agu-bb55x-9jh 32-pin plastic tsop (i) 55 2.7 to 3.6 ? 25 to +85 pd442000agu-bb70x-9jh (8 13.4) (normal bent) 70 pd442000agu-bb85x-9jh 85 pd442000agu-bc70x-9jh 70 2.2 to 3.6 pd442000agu-bc85x-9jh 85 pd442000agu-bc10x-9jh 100 pd442000agu-dd85x-9jh 85 1.8 to 2.2 pd442000agu-dd10x-9jh 100 pd442000agu-dd12x-9jh 120 pd442000agu-bb55x-9kh 32-pin plastic tsop (i) 55 2.7 to 3.6 pd442000agu-bb70x-9kh (8 13.4) (reverse bent) 70 pd442000agu-bb85x-9kh 85 pd442000agu-bc70x-9kh 70 2.2 to 3.6 pd442000agu-bc85x-9kh 85 pd442000agu-bc10x-9kh 100 pd442000agu-dd85x-9kh 85 1.8 to 2.2 pd442000agu-dd10x-9kh 100 pd442000agu-dd12x-9kh 120
data sheet m14669ej7v0ds 3 pd442000a-x pin configurations /xxx indicates active low si gnal. 32-pin plastic tsop (i) (8 13.4) (normal bent) [ pd442000agu-9jh ] marking side a11 a9 a8 a13 /we ce2 a15 v cc a17 a16 a14 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a0 to a17 : address inputs i/o1 to i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground remark refer to package drawings for the 1-pin index mark.
data sheet m14669ej7v0ds 4 pd442000a-x 32-pin plastic tsop (i) (8 13.4) (reverse bent) [ pd442000agu-9kh ] marking side /oe a10 /ce1 i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 /we ce2 a15 v cc a17 a16 a14 a12 a7 a6 a5 a4 a0 to a17 : address inputs i/o1 to i/o8 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable v cc : power supply gnd : ground remark refer to package drawings for the 1-pin index mark.
data sheet m14669ej7v0ds 5 pd442000a-x block diagram address buffer address buffer row decoder memory cell array 2,097,152 bits input data controller a0 a17 sense amplifier / switching circuit column decoder /ce1 /we /oe ce2 output data controller v cc gnd i/o1 i/o8 truth table /ce1 ce2 /oe /we mode i/o supply current h not selected high-z i sb l not selected high-z l h h h output disable high-z i cca l h l h read d out lh lwrite d in remark : v ih or v il
data sheet m14669ej7v0ds 6 pd442000a-x electrical specifications absolute maximum ratings parameter symbol condition rating unit -bb55x, -bb70x, -bb85x -dd85x, -dd10x, -dd12x -bc70x, -bc85x, -bc10x supply voltage v cc ?0.5 note to +4.0 ?0.5 note to +2.7 v input / output voltage v t ?0.5 note to v cc +0.4 (4.0 v max.) ?0.5 note to v cc +0.4 (2.7 v max.) v operating ambient temperature t a ?25 to +85 ?25 to +85 c storage temperature t stg ?55 to +125 ?55 to +125 c note ?3.0 v (min.) (pulse width : 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition -bb55x,-bb70x,-bb85x -bc70x,-bc85x,-bc10x -dd85x,-dd10x,-dd12x unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 2.2 v high level input voltage v ih 2.7 v v cc 3.6 v 2.4 v cc +0.4 2.4 v cc +0.4 ? ? v 2.2 v v cc < 2.7 v ? ? 2.0 v cc +0.3 ? ? 1.8 v v cc < 2.2 v ? ? ? ? 1.6 v cc +0.2 low level input voltage v il ?0.3 note +0.5 ?0.3 note +0.4 ?0.2 note +0.2 v operating ambient t a ?25 +85 ?25 +85 ?25 +85 c temperature note ?1.0 v (min.) (pulse width : 20 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are not 100% tested.
data sheet m14669ej7v0ds 7 pd442000a-x dc characteristics (recommended operating conditions unless otherwise noted) (1/2) parameter symbol test condition -bb55x, -bb70x, -bb85x unit min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /ce1 = v ih or ?1.0 +1.0 a ce2 = v il or /we = v il or /oe = v ih operating supply current i cca1 /ce1 = v il , ce2 = v ih , cycle time = 55 ns ? 35 ma minimum cycle time, cycle time 70 ns ? 30 i i/o = 0 ma i cca2 /ce1 = v il , ce2 = v ih ,?4 cycle time = , i i/o = 0 ma i cca3 /ce1 0.2 v, ce2 v cc ? 0.2 v, ? 4 cycle time = 1 s, i i/o = 0 ma, v il 0.2 v, v ih v cc ? 0.2 v standby supply current i sb /ce1 = v ih or ce2 = v il ?0.35ma i sb1 /ce1 v cc ? 0.2 v, ce2 v cc ? 0.2 v 0.1 2 a i sb2 ce2 0.2 v 0.1 2 high level output voltage v oh i oh = ?0.5 ma 2.4 v low level output voltage v ol i ol = 1.0 ma 0.4 v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classification.
data sheet m14669ej7v0ds 8 pd442000a-x dc characteristics (recommended operating conditions unless otherwise noted) (2/2) parameter symbol test condition -bc70x, -bc85x, -bc10x -dd85x, -dd10x, -dd12x unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /ce1 = v ih or ?1.0 +1.0 ?1.0 +1.0 a ce2 = v il or /we = v il or /oe = v ih operating supply current i cca1 /ce1 = v il , ce2 = v ih ,?30??ma minimum cycle time, v cc 2.7 v ? 25 ? ? i i/o = 0 ma v cc 2.2 v ? ? ? 15 i cca2 /ce1 = v il , ce2 = v ih ,?4?? cycle time = , v cc 2.7 v ? 2 ? ? i i/o = 0 ma v cc 2.2 v ? ? ? 1 i cca3 /ce1 0.2 v, ce2 v cc ? 0.2 v, ? 4 ? ? cycle time = 1 s, i i/o = 0 ma, v il 0.2 v, v cc 2.7 v ? 3 ? ? v ih v cc ? 0.2 v v cc 2.2 v ? ? ? 3 standby supply current i sb /ce1 = v ih or ce2 = v il ?0.35 ? ?ma v cc 2.7 v ? 0.35 ? ? v cc 2.2 v ? ? ? 0.35 i sb1 /ce1 v cc ? 0.2 v, 0.1 2 ? ? a ce2 v cc ? 0.2 v v cc 2.7 v 0.08 2 ? ? v cc 2.2 v ? ? 0.05 1.5 i sb2 ce2 0.2 v 0.1 2 ? ? v cc 2.7 v 0.08 2 ? ? v cc 2.2 v ? ? 0.05 1.5 high level output voltage v oh i oh = ?0.5 ma 2.4 ? v v cc 2.7 v 1.8 ? v cc 2.2 v ? 1.5 low level output voltage v ol i ol = 1.0 ma 0.4 ? v v cc 2.7 v 0.4 ? v cc 2.2 v ? 0.4 remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of product classification.
data sheet m14669ej7v0ds 9 pd442000a-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load [ -bb55x, -bb70x, -bb85x ] 1ttl + 50 pf [ -bc70x, -bc85x, -bc10x, -dd85x, -dd10x, -dd12x ] 1ttl + 30 pf
data sheet m14669ej7v0ds 10 pd442000a-x read cycle (1/3) parameter symbol v cc 2.7 v unit condition -bb55x -bb70x -bb85x min. max. min. max. min. max. read cycle time t rc 55 70 85 ns address access time t aa 55 70 85 ns note 1 /ce1 access time t co1 55 70 85 ns ce2 access time t co2 55 70 85 ns /oe to output valid t oe 30 35 40 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low-z t lz1 10 10 10 ns note 2 ce2 to output in low-z t lz2 10 10 10 ns /oe to output in low-z t olz 555ns /ce1 to output in high-z t hz1 20 25 30 ns ce2 to output in high-z t hz2 20 25 30 ns /oe to output in high-z t ohz 20 25 30 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. read cycle (2/3) parameter symbol v cc 2.2 v unit condition -bc70x -bc85x -bc10x min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns note 1 /ce1 access time t co1 70 85 100 ns ce2 access time t co2 70 85 100 ns /oe to output valid t oe 35 40 50 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low-z t lz1 10 10 10 ns note 2 ce2 to output in low-z t lz2 10 10 10 ns /oe to output in low-z t olz 555ns /ce1 to output in high-z t hz1 25 30 35 ns ce2 to output in high-z t hz2 25 30 35 ns /oe to output in high-z t ohz 25 30 35 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf.
data sheet m14669ej7v0ds 11 pd442000a-x read cycle (3/3) parameter symbol v cc 1.8 v unit condition -dd85x -dd10x -dd12x min. max. min. max. min. max. read cycle time t rc 85 100 120 ns address access time t aa 85 100 120 ns note 1 /ce1 access time t co1 85 100 120 ns ce2 access time t co2 85 100 120 ns /oe to output valid t oe 40 50 60 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low-z t lz1 10 10 10 ns note 2 ce2 to output in low-z t lz2 10 10 10 ns /oe to output in low-z t olz 555ns /ce1 to output in high-z t hz1 30 35 40 ns ce2 to output in high-z t hz2 30 35 40 ns /oe to output in high-z t ohz 30 35 40 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf.
data sheet m14669ej7v0ds 12 pd442000a-x read cycle timing chart t hz2 t rc t oh t hz1 t lz2 t co2 t lz1 t co1 t aa high-z data out ce2 (input) /ce1 (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
data sheet m14669ej7v0ds 13 pd442000a-x write cycle (1/3) parameter symbol v cc 2.7 v unit condition -bb55x -bb70x -bb85x min. max. min. max. min. max. write cycle time t wc 55 70 85 ns /ce1 to end of write t cw1 50 55 70 ns ce2 to end of write t cw2 50 55 70 ns address valid to end of write t aw 50 55 70 ns address setup time t as 000ns write pulse width t wp 45 50 55 ns write recovery time t wr 000ns data valid to end of write t dw 25 30 35 ns data hold time t dh 000ns /we to output in high-z t whz 20 25 30 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf. write cycle (2/3) parameter symbol v cc 2.2 v unit condition -bc70x -bc85x -bc10x min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /ce1 to end of write t cw1 55 70 80 ns ce2 to end of write t cw2 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 000ns write pulse width t wp 50 55 60 ns write recovery time t wr 000ns data valid to end of write t dw 30 35 40 ns data hold time t dh 000ns /we to output in high-z t whz 25 30 35 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf.
data sheet m14669ej7v0ds 14 pd442000a-x write cycle (3/3) parameter symbol v cc 1.8 v unit condition -dd85x -dd10x -dd12x min. max. min. max. min. max. write cycle time t wc 85 100 120 ns /ce1 to end of write t cw1 70 80 100 ns ce2 to end of write t cw2 70 80 100 ns address valid to end of write t aw 70 80 100 ns address setup time t as 000ns write pulse width t wp 55 60 85 ns write recovery time t wr 000ns data valid to end of write t dw 35 40 60 ns data hold time t dh 000ns /we to output in high-z t whz 30 35 40 ns note output active from end of write t ow 555ns note the output load is 1ttl + 5 pf.
data sheet m14669ej7v0ds 15 pd442000a-x write cycle timing chart 1 (/we controlled) t wc t cw1 t whz t dw t dh t ow indefinite data out high-z high-z data in indefinite data out address (input) /ce1 (input) i/o (input / output) ce2 (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
data sheet m14669ej7v0ds 16 pd442000a-x write cycle timing chart 2 (/ce1 controlled) t wc t as t cw1 t dw t dh data in high-z address (input) /ce1 (input) i/o (input) high-z ce2 (input) t cw2 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2.
data sheet m14669ej7v0ds 17 pd442000a-x write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t dw t dh data in high-z address (input) ce2 (input) i/o (input) high-z /ce1 (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1, /we, and a high level ce2.
data sheet m14669ej7v0ds 18 pd442000a-x low v cc data retention characteristics (t a = ?25 to +85 c) parameter symbol test condition -bb55x, -bb70x, -bb85x -bc70x,-bc85x, -bc10x - dd85x,-dd10x, -dd12x unit min. typ. max. min. typ. max. min. typ. max. data retention v ccdr1 /ce1 v cc ? 0.2 v, 1.0 3.6 1.0 3.6 1.0 2.2 v supply voltage ce2 v cc ? 0.2 v v ccdr2 ce2 0.2 v 1.0 3.6 1.0 3.6 1.0 2.2 data retention i ccdr1 v cc = 1.2 v, /ce1 v cc ? 0.2 v, 0.05 1 0.05 1 0.05 1 a supply current ce2 v cc ? 0.2 v i ccdr2 v cc = 1.2 v, ce2 0.2 v 0.05 1 0.05 1 0.05 1 chip deselection t cdr 000ns to data retention mode operation t r t rc note t rc note t rc note ns recovery time note t rc : read cycle time
data sheet m14669ej7v0ds 19 pd442000a-x data retention timing chart (1) /ce1 controlled v ih (min.) v ccdr (min.) v il (max.) /ce1 /ce1 note t cdr data retention mode t r v cc note 2.7 v (-bb55x, -bb70x, -bb85x), 2.2 v (-bc70x, -bc85x, -bc10x), 1.8 v (-dd85x, -dd10x, -dd12x) remark on the data retention mode by controlling /ce1, the input level of ce2 must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state. (2) ce2 controlled v ih (min.) v ccdr (min.) v il (max.) ce2 ce2 0.2 v gnd v cc (min.) note t cdr data retention mode t r v cc note 2.7 v (-bb55x, -bb70x, -bb85x), 2.2 v (-bc70x, -bc85x, -bc10x), 1.8 v (-dd85x, -dd10x, -dd12x) remark on the data retention mode by controlling ce2, the other pins (/ce1, address, i/o, /we, /oe) can be in high impedance state.
data sheet m14669ej7v0ds 20 pd442000a-x package drawings 32-pin plastic tsop( i ) (8x13.4) notes 1. each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters p32gu-50-9jh-2 b 0.45 max. c 0.5 (t.p.) detail of lead end a 8.0 0.1 h 12.4 0.2 b t d 0.22 0.05 g 1.0 0.05 i 11.8 0.1 j 0.8 0.2 k l 0.5 m 0.08 n 0.08 q 0.1 0.05 p 13.4 0.2 s 1.2 max. r3 t 0.25 u 0.6 0.15 + 5 ? 3 2. "a" excludes mold flash. (includes mold flash : 8.3 mm max.) m u l r q s dm c g j 0.145 + 0.025 ? 0.015 1 16 32 17 s s n k h p i a
data sheet m14669ej7v0ds 21 pd442000a-x + 0.025 ? 0.015 32-pin plastic tsop( i ) (8x13.4) notes 1. each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters p32gu-50-9kh-2 b 0.45 max. c 0.5 (t.p.) detail of lead end a 8.0 0.1 h 12.4 0.2 t d 0.22 0.05 g 1.0 0.05 i 11.8 0.1 j 0.8 0.2 k l 0.5 m 0.08 n 0.08 q 0.1 0.05 p 13.4 0.2 s 1.2 max. r3 t 0.25 u 0.6 0.15 + 5 ? 3 2. "a" excludes mold flash. (includes mold flash : 8.3 mm max.) u l r q s 0.145 1 16 32 17 s n s b m d m c g a k h p ij
data sheet m14669ej7v0ds 22 pd442000a-x recommended soldering conditions please consult with our sales offices for soldering conditions of the pd442000a-x. types of surface mount device pd442000agu-9jh : 32-pin plastic tsop (i) (8 13.4) (normal bent) pd442000agu-9kh : 32-pin plastic tsop (i) (8 13.4) (reverse bent)
data sheet m14669ej7v0ds 23 pd442000a-x revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 6th edition/ pp.6, 7 pp.6, 7 modification dc characteristics -bb55x,-bb70x,-bb85x(max.) : i sb = 0.6ma 0.35ma jul. 2002 -bc70x,-bc85x,-bc10x(max.) : i sb = 0.6ma 0.35ma -bc70x,-bc85x,-bc10x(max.) : i sb (v cc 2.7 v) = 0.6ma 0.35ma -dd85x,-dd10x,-dd12x(max.) : i sb = 0.6ma 0.35ma p.8 p.8 modification ac characteristics integration of input waveform and output waveform 7th edition/ pp.2, 4, 21-22 pp.2, 3, 19-20 addition ordering information, 32-pin plastic tsop (i) (8 13.4) (reverse bent) oct. 2002 pin configurations, pd442000agu-***-9kh package drawings, *** : speed grades recommended bb55x, bb70x, bb85x, bc70x, bc85x, bc10x, soldering conditions dd85x, dd10x, dd12x
data sheet m14669ej7v0ds 24 pd442000a-x [ memo ]
data sheet m14669ej7v0ds 25 pd442000a-x [ memo ]
data sheet m14669ej7v0ds 26 pd442000a-x [ memo ]
data sheet m14669ej7v0ds 27 pd442000a-x notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd442000a-x m8e 00. 4 the information in this document is current as of october, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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